In present computer systems, a main memory accessible in both read and write operations (e.g., random access memory (RAM)) is typically implemented by using one or more memory modules which each comprise a plurality of memory devices each implemented on a single semiconductor chip. In particular, these memory devices or memory chips may be, for example, double data rate type (DDR-type). For operating the memory, data communication is not only between a memory controller and the memory modules, but also between the different memory devices of a memory module. For this purpose, the memory devices are provided with a plurality of communication blocks for receiving data from other memory devices or the memory controller and transmitting data to other memory devices or the memory controller. In order to achieve a high data bandwidth for the operation of the memory, high speed serial communication links are used for the data transfer.
In the memory device, the communication blocks are typically positioned at different locations (i.e., the communication blocks are distributed in the memory device). Therefore, clock signals are distributed in the memory device so as to allow for generating the required sampling clock signals for receiving and transmitting data.
FIG. 9 illustrates an on-chip clock distribution network of a conventional memory device. As illustrated, the memory device comprises a plurality of communication blocks 112, 113, 114, 115 which are distributed in the memory device (i.e., positioned at different locations on the semiconductor chip of the memory device). Further, the memory device comprises a main clock generating unit 110 which receives an external reference clock CLK_IO and further external clock signals CLK_RS, CLK_RP for distribution in the memory device. The reference clock signal CLK_IO is typically received from a memory controller or an external clock source. The clock signals CLK_RS and CLK_RP are typically received from other memory devices.
Each of the communication blocks comprises a receiver and a transmitter. In particular, a first communication block 112 comprises a primary transmitter RP and a secondary receiver RS. A second communication block 113 comprises a primary receiver RP and a secondary transmitter TS. Similarly, a third communication block 114 comprises a secondary receiver RS and a primary transmitter TP, and a fourth communication block comprises a primary transmitter TP and a secondary receiver RS.
In the communication blocks 113 and 115, the primary receiver RP receives data from the memory controller or from a previous memory device in a daisy-chain configuration. The secondary transmitter TS transmits data to a next memory device of the daisy-chain configuration. In the communication blocks 112 and 114, the secondary receiver RS receives data from the next memory device of the daisy-chain configuration and the primary transmitter TP transmits data to the previous memory device of the daisy-chain configuration or to the memory controller.
Each of the communication blocks 112, 113, 114, 115 comprises two local clock generating units 120, one for the receiver RP, RS and the other for the transmitter TP, TS. The local clock generating units 120 generate a sampling clock signal SCLK for the receiver RP, RS or for the transmitter TP, TS.
The clock distribution as illustrated in FIG. 10 is based on a master delay-locked loop (MDLL) in the main clock generating unit 110 and slave delay line (SDLL) 122 in each of the local clock generating units 120.
The MDLL comprises a delay chain which receives as its input signal the reference clock signal CLK_IO and generates a delayed output signal. The MDLL further comprises a phase detector which compares the delayed output signal of the delay chain with the reference clock signal and generates an internal control signal so as to adjust the delay of the delay chain. On the basis of the internal delay control signal, a control signal CS is generated which is distributed to each of the local clock generating units 120. The SDLLs 122 in the local clock generating units 120 comprise a delay chain which is configured substantially identical to the delay chain of the MDLL in the main clock generating unit 110 and are adjusted by the control signal CS to provide a delay which substantially corresponds to the delay of the MDLL in the main clock generating unit 110.
To the SDLLs 122 of the local clock generating units 120, a corresponding input clock signal is supplied which is delayed by a SDLL 122 so as to provide a local clock signal having a predetermined phase relationship with respect to the input clock signal of the SDLL. In case of the primary receivers RP, the input clock signal of the corresponding SDLL 122 is formed by the clock signal CLK_RP. In case of the secondary receivers RS, the input clock signal of the corresponding SDLL 122 is formed by the clock signal CLK_RS. In case of the primary and secondary transmitters TP, TS, the input clock signal of the corresponding SDLL 122 is formed by an internal clock signal CLK_IN. A multiplexer 116 selects the internal clock signal CLK_IN of the memory device from the reference clock signal CLK_IO and from the externally supplied clock signal CLK_RP. Output clock signals CLK_TP and CLK_TS are generated on the basis of an output signal of a main clock generating unit 110 so as to have a predetermined phase relationship with respect to the reference clock signal CLK_IO.
Each of the local clock generating units 120 further comprises a phase interpolator 124 so as to generate the sampling clock signal SCLK for the corresponding receiver RS or transmitter TP on the basis of the local clock signal provided by the SDLL 122. Therefore the SDLL 122 is configured to provide at least two local clock signals as output signals of its delay chain, each of the local clock signals having a predetermined phase relationship with respect to the input clock signal of the SDLL 122. By interpolating these at least two local clock signals, the phase relationship of the sampling clock signal SCLK with respect to the input clock signal of the SDLL can be adjusted in response to a corresponding phase control signal CT1-CT8 of the phase interpolator 124. Similarly, the output clock signals CLK_TP and CLK_TS are generated on the basis of a local output clock signal of the MDLL in the main clock generating unit 110 by phase interpolation in response to control signals CT9 and CT10, respectively, via phase interpolators 118.
With the above-described conventional approach for locally generating sampling clock signals in the communication blocks of the memory device there exist, however, problems as to a complex distribution of both clock and control signals. In particular, not only the clock signals CLK_IN, CLK_RS, and CLK_RP have to be distributed within the memory device, but also the control signal CS. This may cause problems with respect to disturbances due to insufficient isolation between lines on the semiconductor chip or may result in a poor signal quality, in particular when the clock and control signals have to be distributed over long distances on the semiconductor chip of the memory device.
In view of the above, there is a need for the present invention.